| |
Semiconductor Testers from Thermo Fisher Scientific
ESD-Tester - Manual
| |
Model |
No. of PINs |
Testing mode |
Description
|
 |
Pegasus
|
2
|
HMM
|
• Manual - No PC
necessary
• HBM-Test up to 12 kV
• full compliant HMM according to IEC 61000-4-2
• max. 5 power supplies for components |
ESD-/Latch-Up-Testers - automated
| |
Model |
No. of PINs |
Testing mode |
Description |
|
ZapMaster MK.1 |
64- 256 |
HBM
MM
Latch-Up (static) |
• automated
• HBM-Tests from 50 V to 8 kV in programmable 1 V-Steps
• MM-Tests from 50 V to 2 kV in programmable 1 V-Steps
• up to 6 power supplies for components
• Testing of multiple components in parallel
• all ZapMaster-Test-Fixtures can be used with 256 Pins and Verifier-Test-Fixtures |
|
ZapMaster MK.2 |
128-
768 |
HBM
MM
Latch-Up |
• automated
• HBM-Tests from 50 V to 8 kV in programmable 1 V-Steps
• MM-Tests from 50 V to 2 kV in programmable 1 V-Steps
• up to 6 power supplies for components
• Testing of multiple components in parallel
• all ZapMaster-Test-Fixtures can be used with 256 Pins and Verifier-Test-Fixtures |
|
ZapMaster MK.4 |
1152
1728
2304 |
HBM
MM
Latch-Up |
• automated
• HBM-Tests from 50 V to 8 kV
• MM-Tests from 25 V to 2 kV
• 256k vectors per pin with read-back up to 10 MHz
• up to 8 power supplies for components (V/I)
• Testing of multiple components in parallel |
|
Orion
|
DUT-Dimensions: 10,2 cm x 10,2 cm
|
CDM
|
• automated
• DUT-Monitoring on the PC-Monitor
• Test up tp 1kV, optional: 2kV |
TLP-/ ESD-Testers
| |
Model |
No. of PINs |
Testing mode |
Description |
|
Celestron |
1 Port |
TLP
HBM
MM
|
• TLP Test System
• TDR, TDR-O, TDR-S, TDT, TDRT, 500 Ohm current source
• Pulswidths from 1,2 to 10 ns
• Rise times 100 ps to 2 ns
• Currents in 50 ohm 10 A
• VF-TLP (optional)
• HBM up to 4 kV (optional)
• MM up to 400 V (optional) |
| Explanations |
| HBM |
Human Body Model, Simulation of the Discharge of a Human Body in a component |
| MM |
Machine Model, Simulation of the Discharge of a conductive device in a component |
| CDM |
Charged Device Model |
| TLP |
Transmission Line Pulsing |
| Latch-Up |
condition that exists within a CMOS device after its internal parasitic SCR
(Silicon Controlled Rectifier) has been triggered into conduction |
| DUT |
Device Under Test |
| Curve Tracing |
Measurement of the input characteritic curve of a component pin |
| Vectoring |
application of sequence of digital signals at a input pin, to set it into a defined state |
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